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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1992 Revised November 1999
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT374CSC 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC 74ABT374CPC Package Number M20B M20D MSA20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description
(c) 1999 Fairchild Semiconductor Corporation
DS011510
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74ABT374
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.
Function Table
Inputs OE H H H H L L L L CP H D L H L H L H L H Internal Outputs Q NC NC L H L H NC NC O Z Z Z Z L H NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data Function

H H
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT374
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) -500 mA 10V -150 mA twice the rated IOL (mA) -0.5V to 5.5V -0.5V to VCC -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65C to +150C -55C to +125C -55C to +150C
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 4)
Note 3: For 8-bit toggling, ICCD <0.8 mA/MHz. Note 4: Guaranteed, but not tested.
Min 2.0
Typ
Max
Units V
VCC
Conditions Recognized HIGH Signal Recognized LOW Signal
0.8 -1.2 2.5 2.0 0.55 1 1 7 -1 -1 4.75 10 -10 -100 -275 50 100 50 30 50 2.5 2.5 2.5
V V V V V A A A V A A mA A A A mA A mA mA mA mA/ Max Min Min Min Min Max Max Max 0.0
IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 A, All Other Pins Grounded
0 - 5.5V VOUT = 2.7V; OE = 2.0V 0 - 5.5V VOUT = 0.5V; OE = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others VCC or GND All Outputs HIGH All Outputs LOW OE = VCC; All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs OPEN OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle
No Load 0.30
MHz
Max
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74ABT374
DC Electrical Characteristics
(SOIC package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.3 2.5 2.0 Min Typ 0.5 -0.9 3.0 1.6 1.3 0.8 Max 0.8 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 5) TA = 25C (Note 5) TA = 25C (Note 6) TA = 25C (Note 7) TA = 25C (Note 7)
Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package) TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 150 2.0 2.0 1.5 1.5 1.5 1.5 VCC = +5.0V CL = 50 pF Typ 200 3.2 3.3 3.1 3.1 3.6 3.4 5.0 5.0 5.3 5.3 5.4 5.4 Max TA = -55C to +125C VCC = 4.5V to 5.5V CL = 50 pF Min 150 1.4 2.0 0.8 1.5 1.3 1.0 6.6 7.6 5.7 7.2 7.2 7.0 Max TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Min 150 2.0 2.0 1.5 1.5 1.5 1.5 5.0 5.0 5.3 5.3 5.4 5.4 Max MHz ns ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP HIGH or LOW 1.5 1.5 1.0 1.0 3.0 3.0 Max TA = -55C to +125C V CC = 4.5V to 5.5V CL = 50 pF Min 2.5 2.5 2.5 2.5 3.3 3.3 Max TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Min 1.0 1.5 1.0 1.0 3.0 3.0 Max ns ns ns Units
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74ABT374
Extended AC Electrical Characteristics
(SOIC Package) TA = -40C to +85C VCC = 4.5V to 5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 8) Min tPLH tPHL tPZH tPZL tPHZ tPZL Output Disable Time Propagation Delay CP to On Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Max 5.7 5.7 6.2 6.2 5.5 5.5 Min 2.0 2.0 2.0 2.0 (Note 11) Max 7.8 7.8 8.0 8.0 Min 2.0 2.0 2.0 2.0 (Note 11) TA = -40C to +85C VCC = 4.5V to 5.5V CL = 250 pF (Note 9) TA = -40C to +85C VCC = 4.5V to 5.5V CL = 250 pF 8 Outputs Switching (Note 10) Max 10.0 10.0 10.5 10.5 ns ns ns Units
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 16)
TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF 8 Outputs Switching (Note 12) Max TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 13) Max 1.8 1.8 4.3 4.3 4.6 ns ns ns ns ns Units
(SOIC Package)
Symbol
Parameter
tOSHL (Note 14) tOSLH (Note 14) tPS (Note 13) tOST (Note 14) tPV (Note 15)
Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions
1.0 1.0 1.8 2.0 2.5
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Symbol CIN COUT (Note 17) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 Units pF pF V CC = 0V V CC = 5.0V Conditions (TA = 25C)
Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT374
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns
FIGURE 2. VM = 1.5V
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MO-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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